1. Field of the Invention
This invention relates to electronic timing circuits and more particularly to circuits that will delay timing signals precisely and continuously with respect to another timing signal.
2. Description of Related Art
Delay lines and silicon delay circuits are well known in the art. Delay lines generally are circuits composed of resistors, capacitors and/or inductors coupled to semiconductor amplifiers or buffers. The signal at the output of the delay line will be delayed by a period of time determined by the reactances of the resistive, capacitive, and/or inductive circuit.
Most delay lines currently are hybrid circuits that are not capable of integration on semiconductor chips.
Silicon delay circuits, while often termed silicon delay lines, are often formed of a chain of simple inverter circuits. The total delay of the chain will be the composite delay of the individual inverter circuits.
A second silicon delay circuit is a silicon timed circuit such as the DS1000-20 from Dallas Semiconductor Corporation, Dallas, Tex. Refer now to FIGS. 1a-1e to discuss the operation of the silicon delay line or silicon timed circuit. An input 5 is connected to an inverting buffer 10a. The output of the inverting buffer 10a is connected to the delay element 20a . As a signal is placed at the input 5, it is inverted and buffered by the inverting buffer 10a. The signal at the output of the inverter buffer 10a is then delayed by some period of time t.sub.d before being available at the output terminal of the delay element 20a. The output terminal of the delay element 20a will be connected to the input of the inverter buffer 30a. The output of the inverter buffer 30a will have the output signal OUT1. Referring now FIG. 1e, it can be seen that output OUT1 is a replica of the input 5 except delayed by a period of time t.sub.d.
The output of the delay element is, also, the input to the inverter buffer 10b and the output of the inverter buffer 10b is the input to the delay element 20b. Delay element 20b, like delay element 20a, will delay a signal placed at it input by a period of time t.sub.d. The output of the delay element 20b is the input of the inverter buffer 30b. The output of the inverter buffer 30b will be the signal OUT2. As can be seen from FIG. 1e, the signal OUT2 will be a replica of the input signal delayed by a time period that is twice the delay period t.sub.d.
A delay segment is composed of the inverter buffer such as inverter buffer 10b, a delay element such as delay element 20b, and an inverter buffer 30b. Multiple delay segments will be serially linked. The last delay segment of a multiple tapped delay line will be the delay segment that has the inverter buffer 10c, the delay element 20c, and the inverter buffer 30c. The output of the inverter buffer 30c will form the output signal OUTn. The digit n indicates the number of delay segments in the multitapped silicon delay line. In the example of the DS1000-20, the number n of delay segments is five and the delay t.sub.d per segment is 4 nsec.
In most delay lines the time delay per segment is nominally equal, with the variation being only due to process variation. This allows for a multiple phased clocking as shown in FIG. 1e to be generated. Each output phase OUT1, OUT2, . . . , OUTn is formed by delaying the input signal by the delay of each delay segment to form each phase of the clock.
The delay elements 20a, 20b, and 20c are illustrated in FIG. 1b as the delay element 20. The input 105 is applied to the rising edge ramp generator 110 and is inverted by inverter buffer 107 and applied to the falling edge ramp generator 112. The output of the rising edge generator 110 is the input to the noninverting terminal of the rising edge comparator 114. The output of the falling edge ramp generator 112 is the input to the noninverting input of the falling edge comparator 115.
The inverting inputs of the rising edge and falling edge comparators 114 and 115 are connected to a reference voltage source V.sub.ref. The output of the rising edge comparator 114 is connected to the set input s of the latch 116 and the output of the falling edge comparator 115 is connected to the reset input r of the latch 116.
The outputs of the rising edge comparator 114 or the falling edge comparator 115 will respectively change from a first logic level (0) to a second logic level (1) when the voltage of the output of the rising edge ramp generator 110 or the falling edge ramp generator 112 have exceeded the voltage level of the reference voltage source V.sub.ref. Conversely, when the voltage level of the input of the rising edge ramp generator 110 or the falling edge ramp generator 112 is less than the voltage level of the reference voltage source V.sub.ref, the output of the rising edge comparator 114 or the falling edge comparator 115 will change from the second logic level (1) to the first logic level (0).
The output Q of the latch 116 will be set to the second logic level (1) if the set s of the latch 116 is brought to the second logic level (1), while the reset input r remains at the first logic level (0) and the output Q of the latch 116 will assume the first logic level (0) when the reset input r is brought to the second logic level (1) and the set input s is brought to the first logic level (0).
Refer now to FIG. 1c to understand the operation of the rising edge and falling edge ramp generators 110 and 112. The rising edge and falling edge ramp generators 110 and 112 each have an input 109 connected to the gate of the metal oxide semiconductor (MOS) transistor M.sub.1 120. The source of the MOS transistors M.sub.1 120 is connected to the ground reference point and the drain is connected to the output of the output of the ramp generators 110 or 112. The constant current source 122 is connected between the power supply voltage source V.sub.CC and the output of the ramp generators 110 or 112. Optionally, fuses 126a, 126b, 126c, and 126d each connect the first plate of one of the array of capacitors 125a, 125b, 125c, and 125d to the output of the ramp generators 110 or 112. If the fuses 126a, 126b, 126c, and 126d are not used the first plate of the capacitor 125a, 125b, 125c, and 125d will be attached to the output of the ramp generators 110 or 112, and the delay of the delay elements will be fixed.
The fuses 126a, 126b, 126c, and 126d, if implemented, will be used to select the appropriate capacitor or capacitors of the array of capacitors 125a, 125b, 125c, and 125d. This will set the delay of the delay element as the capacitors 125a, 125b, 125c, and 125d are selected.
When the input 109 of the ramp generator 110 or 112 is at the first logic level (0), the MOS transistor M.sub.1 will not be conducting. The constant current source 122 will be charging the capacitors 125a, 125b, 125c, and 125d. The voltage (V) at the output of the ramp generators 110 or 112 will be: ##EQU1##
where:
I is the current through the constant current source 122. PA1 T is the time elapsed from the time the signal at the input 109 assumed the first logic level (0). PA1 C is the capacitance of the capacitor array 125a, 125b, 125c, and 125d. PA1 d is the time delay of the second clock CLKD from the first clock CLK. PA1 T is the period of the master clock MCLK, the first clock CLK, and the second clock CLKD. PA1 n is the fractional amount of the delay of the period T, and is a positive number greater than unity.
When the input 109 is at the second logic level (1), the MOS transistor M.sub.1 120 is conducting. The voltage at the output of the ramp generators 110 or 112 will fall from the voltage described above toward the level of the ground reference point. The time for this change will depend on the drain to source resistance of the MOS transistor M.sub.1 120 and the value of the capacitance of the capacitor array 125a, 125b, 125c, and 125d.
Refer now to FIG. 1d, for a detailed description of the voltage waveforms detailing the operation of the delay element 20 of FIG. 1b. The input to the delay element will change from the first logic level (0) to the second logic level (1) at time T.sub.1. At this time, the output of the rising edge ramp generator will begin to rise as described in FIG. 1c. Once the voltage level of the output of the rising edge voltage generator attains the level of the reference voltage source V.sub.ref at time T.sub.2, the rising edge comparator will change from the first logic level (0) to the second logic level (1). The output of the latch will be set from the first logic level (0) to the second logic level (1). The time difference from time T.sub.1 to time T.sub.2 will be the delay time t.sub.d.
At time T.sub.3, the input will change from the second logic level (1) to the first logic level (0). At this time, the voltage level at the output of the rising edge generator will start to fall relatively rapidly. When the voltage level at the output of the rising edge ramp generator falls to a level less than that of the reference voltage source V.sub.ref, the output of the rising edge comparator changes from the second logic level (1) to the first logic level (0).
At this same time T.sub.3, the voltage level of the output of the falling edge ramp generator begins to rise. When the voltage level of the output of the falling edge ramp generator attains the level of the voltage of the reference voltage source V.sub.ref, the output of the falling edge comparator will change from the first logic level (0) to the second logic level (1) thus resetting the output of the latch from the second logic level (1) to the first logic level (0). At time T.sub.4, the output of the latch will be reset thus changing from the second logic level (1) to the first logic level (0). The time difference from time T.sub.3 to time T.sub.4 is the delay time t.sub.d.
At the next cycle T.sub.1, as the input changes from the first logic level (0) to the second logic level (1), the voltage level of the falling edge ramp generator will ball rapidly. As the voltage level of the falling edge ramp generator surpasses the voltage level of the reference voltage source, the falling edge comparator will change from the second logic level (1) to the first logic level (0). The changing of the rising edge comparator from the second logic level (1) to the first logic level (0) at time T.sub.3 and the falling edge comparator the second logic level (1) to the first logic level (0) at time T.sub.1, ensures that the latch will never have a set s and a reset r simultaneously at the second level (1) thus creating a metastable condition.
While silicon delay lines as described above are able to be integrated easily on a semiconductor wafer, they do not allow for modification of the delays t.sub.d of the individual delay times t.sub.d of the individual elements.
Referring now to FIG. 1f to examine a situation found developing the timing and clocking for microprocessors and digital signal processors. A master clock MCLK will have a period T. Within the circuit for which the master clock MCLK is providing the timing, a portion of that circuit may require a first clock CLK that has a time delay .DELTA. from the master clock MCLK and a second clock CLKD that has a time delay d from the first clock CLK. The time delay d is a fractional amount of the period or ##EQU2##
where:
Generally, delay d is a 900 phase shift or one quarter of the time T, or in the case with multitapped silicon delay lines, as described above, the increments will be fixed and not adjustable for the requirements of the master clock MCLK.
U.S. Pat. No. 5,103,114 (Fitch) teaches a circuit to develop a clock of a specified duty cycle using standard digital delay lines.
U.S. Pat. No. 5,532,633 (Kawai) discloses a clock generating circuit to generate multiple non-overlapping clock signals. A fundamental clock is delayed to form multiple delayed fundamental clocks. The final delayed fundamental clock is the input to a frequency divider. The frequency divided clock is logically combined with the fundamental clock to form the non-overlapping clock signals.
U.S. Pat. No. 3,961,269 (Alvarez) discloses a multiple phase clock generator that will create multiple phase clocks from a single phase clock. The single phase clock is inverted to provide two complementary signals. The two complementary signals are each one of the inputs to two push-pull amplifiers. The outputs of the push-pull amplifiers are cross-coupled as input to a logic gate that logically combines the output of the cross-coupled amplifier with the opposite phase of the complementary clock to drive a second input of the push-pull amplifier. By judicious selection of the operating parameters, the desired separation and the shape of the two clock phases can be attained.
U.S. Pat. No. 3,590,280 (Hudson et al.) illustrate another design of a multiphase clock. The multiphase clock is derived from a single phase clock and has remotely controllable variable pulsewidths and variable phase shifts. J-K flip-flops and a MOS transistor with resistors and capacitors are utilized to form a monostable multivibrator. The phase can be adjusted by a computer connected to a digital-to-analog converter. The outputs of the digital-to-analog converter are connected to the gates of the MOS transistor to control the timings of the monostable multivibrator.